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INTEGRATED CIRCUITS
DATA SHEET
PCF8813 (67 + 1) x 102 pixels matrix LCD driver
Product specification Supersedes data of 2002 Sep 24 2004 Mar 05
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 8 8.1 8.2 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 10 10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.2 10.3 11 11.1 11.2 11.3 11.4 11.5 11.6 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION I/O buffer and interface Oscillator Address counter Display data RAM Timing generator Display address counter LCD row and column drivers LCD waveforms and DDRAM to data mapping DDRAM addressing Data order Mirror X Mirror Y Bottom row swap Output row order PARALLEL INTERFACES 6800-type parallel interface 8080-type parallel interface SERIAL INTERFACES Serial peripheral interface Write mode Read mode Serial interface (3-line) Write mode Read mode I2C-BUS INTERFACE (Hs-MODE) Characteristics of the I2C-bus (Hs-mode) System configuration Bit transfer Start and stop conditions Acknowledge I2C-bus Hs-mode protocol Command decoder INSTRUCTIONS Initialization Reset function Power-down mode Display Control Set Y address of RAM Set X address of RAM 2 11.7 11.8 11.9 11.10 11.11 11.12 12 13 14 15 16 17 17.1 17.2 17.3 17.4 17.4.1 17.4.2 17.5 17.5.1 17.5.2 17.5.3 17.6 17.7 17.8 17.9 18 18.1 18.2 18.3 19 20 21 22 23 24 25
PCF8813
Set maximum X address or Y address Set display start line, initial start row and row 0 Set normal or partial display mode Free programmable multiplex rate Set HV generator stages Bias system TEMPERATURE COMPENSATION LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS MODULE MAKER PROGRAMMING LCD voltage calibration Manufacturer identity Seal bit One time programming Architecture Operations Interface commands Disable OTP command Module maker calibration Refresh Filling the shift register Programming flow Programming specification Programming examples APPLICATION INFORMATION Protection from light Application examples Chip-on-glass applications DEVICE PROTECTION DIAGRAM BONDING PAD INFORMATION TRAY INFORMATION DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2004 Mar 05
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
1 FEATURES
PCF8813
* Single-chip LCD controller or driver * 67 row + 1 icon row, 102 column outputs (the icon row is available twice to allow icons to be displayed at the top or at the bottom of the display) * Very low power consumption, optimized for battery operated systems * On-chip: - Display data RAM 68 x 102 bits - Configurable voltage multiplier (x 5, x 4, x 3 and x 2) generating highly accurate VLCD and includes booster capacitors (external VLCD is also possible) - Temperature compensation of VLCD with four selectable temperature coefficients - Generation of intermediate LCD bias voltages - Highly-accurate built-in oscillator requiring no external components (an external clock is also possible) * High integration level resulting in minimum number of external capacitors and resistors * Selectable 8-bit parallel interface, 3-line or 4-line Serial Peripheral Interface (SPI), 3-line serial interface and high-speed I2C-bus interface * External reset input * CMOS compatible inputs * Mux rates: 1 : 9 to 1 : 65 in steps of 8 and 1 : 68 * Logic supply voltage range 1.7 to 3.3 V * High voltage generator supply voltage range 2.4 to 4.5 V * Display supply voltage range 3.0 to 9.0 V * One Time Programmable (OTP) VLCD trimming * Horizontal and vertical mirroring * Status read which allows chip recognition and content checking of some registers 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8813U/2DA/2 - DESCRIPTION chip with bumps in tray for COG VERSION - * Start address line which allows, for instance, scrolling of the displayed image * Programmable display RAM pointers for various display sizes * Slim chip layout optimized for chip-on-glass applications * Operating temperature range -40 to +85 C * Very close tolerance on VLCD and frame frequency for excellent optical performance * Support for LCD cell tolerance compensation of VLCD by OTP storage. 2 APPLICATIONS
* Telecom equipment * Portable instruments * Point of sale terminals. 3 GENERAL DESCRIPTION
The PCF8813 is a low power CMOS LCD controller driver designed to drive a graphic display of 67 rows and 102 columns plus an icon row of up to 102 symbols. All necessary functions for the display are provided in a single chip, including on-chip generation of the LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8813 can interface to microcontrollers via a parallel, serial or I2C-bus interface.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
5 BLOCK DIAGRAM
PCF8813
handbook, full pagewidth
VDD1
VDD2
VDD3
C0 to C101
R0 to R67
102 COLUMN DRIVERS BIAS VOLTAGE GENERATOR DATA PROCESSING
68 ROW DRIVERS
VLCDIN VSS1 VSS2 VOTPPROG VLCDSENSE VLCDOUT T1 T2 T3 T4 T5
SHIFT REGISTER
RESET FOUR-STAGE HIGH-VOLTAGE GENERATOR DISPLAY DATA RAM 68 x 102 bits OSCILLATOR
RES
OSC
TIMING GENERATOR ADDRESS COUNTER DISPLAY ADDRESS COUNTER
COMMAND DECODER
PCF8813
I/O BUFFER PARALLEL / SERIAL / I 2C-BUS INTERFACE 3
MGU619
DB7/SDATA
DB6/SCLK
DB5/SDOUT
DB4
DB3/SA1
DB2/SA0
DB1
PS [2:0]
EXT
SDAH
Fig.1 Block diagram.
2004 Mar 05
SCLH/SCE
4
SDAHOUT
R/W/WR
E/RD
DB0
D/C
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
6 PINNING SYMBOL R15 to R0 R16 to R31 C0 to C101 R67 R66 to R48 R32 to R47 R67 SDAHOUT SDAH VDD1 VDD3 VDD2 VDD1 R/W/WR E/RD DB0 DB1 DB2/SA0 DB3/SA1 DB4 DB5/SDOUT DB6/SCLK DB7/SDATA VSS1 D/C SCE/SCLH VOTPPROG VDD1 OSC VSS2 VSS1 T5 T1 T2 PS0 PS1 PS2 VDD1 T4 T3 2004 Mar 05 PAD(1) 7 to 22 23 to 38 39 to 140 141 142 to 160 161 to 176 177 183 184 to 185 186 to 191 192 to 196 197 to 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 to 221 222 to 224 225 226 227 to 236 237 to 246 247 248 249 250 251 252 253 254 255 duplicated LCD row driver output for row 67 (used only for icons) data output for I2C-bus interface; notes 2 and 3 data output for I2C-bus interface; note 2 supply voltage 1; note 4 supply voltage 3; note 4 supply voltage 2; note 4 supply voltage 1; notes 4 and 5 READ/WRITE (6800) or WRITE (8080 interface) input; note 6 LCD column driver outputs LCD row driver output for row 67 (used only for icons) LCD row driver outputs LCD row driver outputs DESCRIPTION
PCF8813
clock enable (6800 interface) or READ (8080 interface) input; note 7 parallel data input/output; note 8 parallel data input/output; note 8 parallel data input/output or I2C-bus slave address input (bit 0) parallel data input/output or I2C-bus slave address input (bit 1) parallel data input/output; note 8 parallel data input/output or serial output (SDOUT) parallel data input/output or output or serial clock input (SCLK) parallel data input/output or serial data input (SDATA) ground voltage 1; notes 5 and 9 data/command; note 10 chip enable or clock input for I2C-bus interface voltage inputs for OTP programming; see note 11 supply voltage 1; notes 4 and 5 oscillator input; note 12 ground voltage 2; note 9 ground voltage 1; note 9 test input 5; note 13 test input 1; note 13 test input 2; note 13 parallel/serial/I2C-bus data input selection pad 0 parallel/serial/I2C-bus data input selection pad 1 parallel/serial/I2C-bus data input selection pad 2 supply voltage 1; notes 4 and 5 test output 4; note 13 test output 3; note 13 5
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PAD(1) 256 to 262 263 to 271 272 273
PCF8813
SYMBOL VLCDIN VLCDOUT VLCDSENSE RES Notes
DESCRIPTION LCD supply voltage input; note 14 generated LCD supply voltage; note 14 voltage multiplier (VLCD) regulation input; note 14 external reset input
1. Dummy pads are located at positions 1, 2, 3, 5, 6, 179, 180, 181, 182 and 274; dummy and alignment pads are located at positions 4 and 178. 2. When not in use, this pad must be connected to VDD1 or VSS1. 3. Output SDAHOUT is used as the data acknowledge output when the I2C-bus is selected. By connecting SDAHOUT to SDAH externally, the SDAH line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in COG applications because where the track resistance from the SDAHOUT pad to the SDAH line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. Therefore it is possible during the acknowledge cycle that the PCF8813 will not create a logic LOW level. By splitting the SDAH input from the SDAHOUT output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid LOW level. 4. VDD2 and VDD3 supply the internal voltage generator, both have the same voltage and may be connected together outside of the chip; VDD1 supplies the remainder of the chip. VDD1, VDD2 and VDD3 can be connected together but then care must be taken with respect to the supply voltage range. If the internal voltage generator is not used, pads VDD2 and VDD3 must be connected to pads VDD1. 5. This pad can be used to tie-off unused input pads to the power supply voltage or to ground. 6. This input is not used in serial and I2C-bus mode and must therefore be connected to either VDD1 or VSS1. 7. This input is not used when the serial or I2C-bus interface is selected and must therefore be connected to VDD1 or VSS1. 8. When serial or I2C-bus mode is selected, the unused parallel pads must be connected to VDD1 or VSS1. 9. Supply rails VSS1 and VSS2 must be connected together. 10. This input is not used with the 3-line serial interface and must therefore be connected to VDD1 or VSS1. 11. This pad can be connected externally to the SCE/SCLH pad to reduce the number of pads routed in COG applications. When not connected in this configuration, VOTPPROG must be connected to either VDD1 or VSS1 after completion of OTP programming and after the seal bit has been set. 12. When the on-chip oscillator is used, the OSC input must be connected to VDD1. If an external clock signal is used, then this is connected to the OSC input. If both the oscillator and external clock are inhibited by connecting pad OSC to VSS1, the display is not clocked and may be in a DC state. To avoid this, the chip should always be put into Power-down mode before stopping the clock. 13. Test pads T1 to T5 are not accessible to users: T1, T2 and T5 must be connected to VSS; T3 and T4 must be open-circuit. 14. Positive power supply for the liquid crystal display (see also Figs 51, 52 and 53): a) If the internal voltage generator is used, pads VLCDIN, VLCDSENSE and VLCDOUT must be connected together. b) An external LCD supply voltage can be supplied using the VLCDIN pad, this requires that pad VLCDOUT is open-circuit, pad VLCDSENSE is connected to the VLCDIN input, and the internal voltage generator is switched off. In Power-down mode, the external LCD supply voltage must be switched off.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
7 7.1 FUNCTIONAL DESCRIPTION I/O buffer and interface 7.5 Timing generator
PCF8813
One of five industrial standard interfaces can be selected using the interface configuration inputs PS2, PS1 and PS0. Table 1 PS2 0 0 0 0 1 1 1 1 7.2 Parallel/serial/I2C-bus interface selection PS1 0 0 1 1 0 1 0 1 Oscillator PS0 0 1 0 1 0 0 1 1 INTERFACE 3-line SPI 4-line SPI 8080 parallel interface 6800 parallel interface high-speed I2C-bus interface
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data buses. 7.6 Display address counter
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off and normal/inverse video) is set by bits D and E in the display control command. 7.7 LCD row and column drivers
3-line serial interface
The PCF8813 contains 68 row and 102 column drivers, which connect the appropriate LCD bias voltages in a sequence to the display in accordance with the data that is to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected.
The on-chip oscillator provides the clock signal for the display system. No external components are required. An external clock signal, if used, is connected to this input. 7.3 Address counter
The Address Counter (AC) assigns addresses to the display data RAM for writing. The X address X[6:0] and the Y address Y[3:0] are set separately. 7.4 Display data RAM
The PCF8813 contains a 68 x 102 bit static RAM which stores the display data. The Display Data RAM (DDRAM) is divided into eight banks of 102 bytes (8 x 8 x 102 bits), one bank of 1 x 3 x 102 bits and a separate bank of 1 x 1 x 102 for icons. During RAM access, data is transferred to the RAM via any of the four interfaces. There is a direct correspondence between the X address and the column output number.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
7.8 LCD waveforms and DDRAM to data mapping
PCF8813
frame n
VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS
frame n + 1 Vstate0(t) Vstate1 (t)
ROW 0 R0 (t)
ROW 1 R1 (t)
COL 0 C0 (t)
COL 1 C1 (t)
VLCD - VSS V3 - VSS VLCD - V2 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD VLCD - VSS V3 - VSS VLCD - V2 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD
Vstate1(t)
Vstate2 (t)
0 1 2 3 4 5 6 7 8...
... 67 0 1 2 3 4 5 6 7 8...
... 67
MGU620
Vstate0(t) = C1(t) - R0(t). Vstate1(t) = C1(t) - R1(t).
Fig.2 Typical LCD driver waveforms.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
DPRAM
bank 0
top of LCD
R0
bank 1 R8
bank 2
R16
LCD
bank 3
R24
bank 8
bank 10
R64
R67
MGU621
Fig.3 Display data RAM.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
7.9 DDRAM addressing
PCF8813
handbook, MSB full pagewidth
0
LSB
MSB MSB 8 10 icon data LSB 0 X address Y address
MGU622
LSB 101
Fig.4 Sequence of writing data bytes into the RAM.
Data is downloaded in bytes into the RAM matrix of the PCF8813 as indicated in Fig.4. The display data RAM has a matrix of 68 by 102 bits. The columns are addressed by the X address pointer whilst the rows are addressed in groups of 8 by the Y address pointer. However, there are only three rows in bank 8 and one row in bank 10. There is no bank 9. Thus the address ranges are: X = 0 to 101 (1100101) and Y = 0 to 8 and then 10 (1010). The PCF8813 is limited to 102 columns by 68 rows, addressing the RAM outside this area is not allowed. Two different addressing modes are possible; horizontal addressing and vertical addressing. In the horizontal addressing mode (V = 0) the X address increments after each byte. After the last X address (X = 101), x wraps-around to 0 and Y increments to address the next row (see Fig.5) until bank 8 is filled. In the vertical addressing mode (V = 1) the Y address increments after each byte. After the Y address (Y = 8), there is Y wraparound to 0 and X increments to address the next column (see Fig.6). After the very last address (X = 101 and Y = 8) the address pointers wraparound to address X = 0 and Y = 0 in both addressing modes. 2004 Mar 05 10
Addressing in bank 10 is a special case as these RAM locations are not automatically accessed. Bank 10 is reserved for icons. Icon locations must be addressed explicitly by setting the Y address pointer to 10. The Y address pointer does not auto-increment when the X address overflows or underflows (it stays in set to bank 9). Writing icon data is independent of the horizontal or vertical addressing (V-bit) but is affected by the Mirror X (MX) and Mirror Y (MY) bits. MX and MY are described in Sections 7.11 and 7.12.
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
0 102 204 306 408 510 612 714 816 918 0
1 103 205 307 409 511 613 715 817 919
2 104 206 308 410 512 614 716 818 icons X address 917 1019 101
0
Y address
8 10
MGU623
Fig.5 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 918 0
9 10
0
Y address
917 icons X address 1019 101
8 10
MGU624
Fig.6 Sequence of writing data bytes into the RAM with vertical addressing (V = 1).
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
7.10 Data order
PCF8813
The Data Order bit (DO) defines the bit order (MSB on top or LSB on top) for writing in the RAM; see Figs 7 and 8.
MSB handbook, full pagewidth
LSB
MSB
MGW739
LSB
Fig.7 Display data RAM byte organisation; DO = 1.
LSB handbook, full pagewidth
MSB
LSB
MGW738
MSB
Fig.8 Display data RAM byte organisation; DO = 0.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
7.11 Mirror X
PCF8813
The MX bit allows horizontal mirroring. When MX = 1, the X address space is mirrored (see Fig.9). The address X = 0 is then located at the right side (column 101) of the display. When MX = 0, mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display (see Fig.10).
handbook, full pagewidth
0
8 10
101
X address Y address
0
MGU626
Fig.9 Display data RAM format addressing; MX = 1.
handbook, full pagewidth
0
8 10
0
X address Y address
101
MGU625
Fig.10 Display data RAM format addressing; MX = 0.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
7.12 Mirror Y
PCF8813
The MY bit allows vertical mirroring. When MY = 1, the Y address space is mirrored resulting in an upside-down display. The address Y = 0 is then located at the bottom of the display (see Fig.11). When MY = 0, the mirroring is disabled and the address Y = 0 is located at top of the display (see Fig.12). A change in the state of MY has an immediate effect on the display and the effect of MY is visible immediately the bit is modified. This feature makes it possible to mount the device at the top or bottom of the display.
handbook, full pagewidth
8
0 10
0
X address Y address
101
MGU628
Fig.11 Display data RAM format addressing; MY = 1.
handbook, full pagewidth
0
8 10
0
X address Y address
101
MGU627
Fig.12 Display data RAM format addressing; MY = 0.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
7.13 Bottom row swap
PCF8813
the end for the icon data. When MY is set to 1, the RAM is still accessed in a linear manner but starting from the last row, counting down to zero and then jumping to the icon data. When N/P is set to 1, the Free Programmable Mux Rate (FPMR) mode is disabled and row addressing is in normal mode (see Section 11.9), therefore counting is the same as for MY = 0 and BRS = 0. When N/P is 0, FPMR mode is enabled. Only 65 rows are addressed/read in FPMR mode. Figures 13 and 14 show the possibility of connecting the icon row (row R67) at the top or bottom of the display.
This mode swaps the order of the order of the rows; see Figs 13 and 14. The mode is useful to aide routing to displays when it is not possible to pass tracks under the device, as in the case of Tape Carrier Packages (TCP). 7.14 Output row order
The order in which the rows are activated is a function of bits Bottom Row Swap (BRS), Mirror Y (MY) and Normal Partial mode (N/P). This has important implications when the device is used either in COG or TCP applications. When MY is set to 0, the RAM is accessed in a linear manner, starting at R0, counting to R66, then jumping to
handbook, full pagewidth
INTERFACE
COLUMNS
R15 R0 R15 R16 R31
Fig.13 Row order and interconnection with BRS = 0, MY = 0 and N/P = 1.
R16 R0
R31
R67
R63
R32 R48
R47
R67 R67 R32
RAM
R47 R48
R63
R66 R67
MGW793
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
INTERFACE
R0 R1 R2
COLUMNS
R66 R35 R66
Fig.14 Row order and interconnection with BRS = 1, MY = 0 and N/P = 1.
R51
R50
R35
R67
R3
R19 R18
R67 R34 R67 R0 R34
RAM
R67
MGW794
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
8 PARALLEL INTERFACES 9 SERIAL INTERFACES
PCF8813
The parallel interface is an 8-bit bidirectional interface for communication between the microcontroller and the LCD driver chip. Two different parallel interfaces can be selected by the inputs PS2, PS1 and PS0. 8.1 6800-type parallel interface
Communication with the microcontroller can also be via a clock-synchronized serial peripheral interface. It is possible to select two different 3-line interfaces (SPI and serial interface) or a 4-line serial interface (SPI). Selection of the interface is made with the inputs PS2, PS1 and PS0 (see Section 7.1). 9.1 Serial peripheral interface
The interface functions of the 6800-type parallel interface are shown in Table 2. Table 2 D/C 0 0 1 1 6800-type parallel interface function R/WR 0 1 0 1 OPERATION command data write read status register display data write none
The Serial Peripheral Interface (SPI) is a 3-line or 4-line interface for communication between the microcontroller and the LCD driver. The 3-line interface requires a chip enable input (SCE), serial clock (SCLK) and serial data (SDATA). For the 4-line serial interface, a separate D/C line is added. The PCF8813 is connected to the serial data I/O (SDATA) of the microcontroller via the pads data input (SDATA) and data output (SDOUT) connected together. 9.1.1 WRITE MODE
The 6800-type parallel interface can be configured to have the clock connected to the Enable input (E) with timing as shown in Fig.38, or with the clock connected to the chip select input (SCE) and the Enable (E) is tied HIGH with timing as shown in Fig.39. The PCF8813 is capable of detecting these different modes automatically. 8.2 8080-type parallel interface
Table 3 shows the interface functions of the 8080-type parallel interface. Table 3 D/C 0 0 1 1 6800-type parallel interface function RD 1 0 1 1 WR 0 1 0 1 OPERATION command data write read status register display data write none
The display data/command indication may be controlled via software or by the D/C select input. When the D/C input is used, display data is transmitted when D/C is HIGH, and command data is transmitted when D/C is LOW (see Figs 15 and 16). When D/C is not used, the display data length instruction is used to indicate that a specific number of display data bytes (1 to 256) are to be transmitted (see Fig.17). The byte that follows the display data string is handled as an instruction command. If SCE is pulled HIGH during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. The next byte received will be handled as an instruction command (see Fig.18).
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
SCE
D/C
SCLK
SDATA
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGW744
Fig.15 Serial bus protocol; transmission of one byte.
handbook, full pagewidth
SCE
D/C
SCLK
SDATA
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGW745
Fig.16 Serial bus protocol; transmission of several bytes.
handbook, full pagewidth
SCE
SCLK
SDATA
DB7 DB6 DB5 DB4
DB2 DB1 DB0 data
data
last data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 instruction
display length instruction and length data (two bytes)
display data string
MGW746
Fig.17 Transmission of several bytes.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
SCE
SCLK
SDATA
data
data
data
data
data
data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
MGW747
display data string
instruction
Fig.18 Transmission interrupted by SCE.
9.1.2
READ MODE
The interface read mode means that the microcontroller reads data from the PCF8813. To do so the microcontroller first has to send a command, the read status command, and then the PCF8813 will respond by transmitting data on the SDOUT line. After that SCE is required to go HIGH before a new command is sent (see Fig.17).
The PCF8813 samples SDATA at rising SCLK edges, but shifts SDOUT data at falling SCLK edges. Thus the microcontroller reads SDOUT data at rising SCLK edges. After the read status command has been sent, the SDATA line must be set to 3-state not later then at the falling SCLK edge of the last bit (see Fig.19).
handbook, full pagewidth
SCE
RES
SCLK
SDATA
DB7 DB6 DB5 DB4 DB3 DB2
DB1 DB0
SDO instruction
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 read out data
MGU629
Fig.19 SPI 3-line and 4-line read mode.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
9.2 Serial interface (3-line)
PCF8813
handbook, full pagewidth
transmission byte (1)
D/C
D7 MSB
D6
D5
D4
D3
D2
D1
D0 LSB
D/C
transmission byte
D/C
transmission byte
D/C
transmission byte
MGW713
(1) A transmission byte may be a command byte or a data byte.
Fig.20 Serial data stream, write mode.
The serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The three lines are: SCE (chip enable), SCLK (serial clock) and SDATA (serial data). The PCF8813 is connected to the SDA of the microcontroller by the SDATA (data input) and SDOUT (data output) pads which are connected together. 9.2.1 WRITE MODE
Figures 21, 22 and 23 show the protocol of the write mode: * When SCE is HIGH, SCLK clocks are ignored; the serial interface is initialized during the HIGH time of SCE (see Fig.21) * At the falling SCE edge SCLK must be LOW (see Fig.41) * SDATA is sampled at the rising edge of SCLK * D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is sampled with the first rising SCLK edge * If SCE stays LOW after the last bit of a command/data byte, the serial interface is ready for the D/C-bit of the next byte at the next rising edge of SCLK (see Fig.22). * A reset pulse with RES interrupts the transmission and the data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C-bit of a command/data byte (see Fig.23).
In the write mode of the interface, the microcontroller writes commands and data to the PCF8813. Each data packet contains a control bit D/C and a transmission byte. If D/C is LOW, the following byte is interpreted as a command byte. If D/C is HIGH, the following byte is stored in the display data RAM. The address counter is incremented automatically after every data byte. Figure 20 shows the general format of the write mode and the definition of the transmission byte. Any instruction can be sent in any order to the PCF8813. The MSB of a byte is transmitted first. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no effect and no power is consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of data transmission.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
SCE
SCLK
SDATA
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGU630
Fig.21 Serial interface (3-line), write mode - control bit followed by a transmission byte.
handbook, full pagewidth
SCE
SCLK
SDATA
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C transmission byte
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C transmission byte
MGU631
Fig.22 Serial interface (3-line), write mode - transmission of several bytes.
handbook, full pagewidth
SCE
RES
SCLK
SDATA
D/C DB7 DB6 DB5 DB4
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D/C
DB7 DB6
MGU632
Fig.23 Serial interface (3-line), write mode - interrupted by reset (RES).
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
9.2.2 READ MODE
PCF8813
handbook, full pagewidth
SCE
SCLK
SDATA
D/C DB7 DB6 DB5 DB4
DB3 DB2 DB1 DB0
D/C
SDOUT
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MGU633
Fig.24 Serial interface (3-line), read mode.
In the read mode of the interface, that the microcontroller reads data from the PCF8813. To do this the microcontroller has first to send a command, then the read status command, and then the PCF8813 will respond by transmitting data on the SDOUT line. After that, SCE is required to go HIGH before a new command is sent (see Fig.24). The PCF8813 samples the SDATA data at rising SCLK edges, but shifts SDOUT data at falling SCLK edges. Thus the microcontroller reads SDOUT data at rising SCLK edges.
After the read status command has been sent, the SDATA line must be set to 3-state not later than at the falling SCLK edge of the last bit. The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge (see Fig.24). The last rising SCLK edge sets SDOUT to 3-state after a delay time (see time t4 in Fig.44).
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
10 I2C-BUS INTERFACE (Hs-MODE) 10.1 Characteristics of the I2C-bus (Hs-mode) 10.1.1 SYSTEM CONFIGURATION
PCF8813
* Transmitter: the device that sends the data to the bus * Receiver: the device that receives the data from the bus * Master: the device which initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronisation: procedure to synchronize the clock signals of two or more devices.
The I2C-bus Hs-mode is for bidirectional, two-line communication between different ICs or modules with speeds up to 3.4 MHz. The only difference between Hs-mode slave devices and Fast-mode slave devices is the speed at which they operate, therefore the buffers on the SLCH and SDAH outputs(1) have an open-drain. This is the same for I2C-bus master devices which have an open-drain SDAH output and a combination of open-drain pull-down and current source pull-up circuits on the SCLH output. Only the current source of one master is enabled at any one time, and only during Hs-mode. Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
(1) In Hs-mode, SCL and SDA lines operating at the higher frequency are referred to as SCLH and SDAH.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.25 System configuration.
10.1.2
BIT TRANSFER
One data bit is transferred during each clock pulse (see Fig.26). The data on the SDAH line must remain stable
during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.26 Bit transfer.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
10.1.3 START AND STOP CONDITIONS
PCF8813
line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P).
Both data and clock lines remain HIGH when the bus is not busy (see Fig.27). A HIGH-to-LOW transition of the data
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.27 Definition of start and stop conditions.
10.1.4
ACKNOWLEDGE
Each byte of eight bits is followed by an acknowledge bit (see Fig.28). The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.28 Acknowledge on the I2C-bus.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
10.2 I2C-bus Hs-mode protocol
PCF8813
selected slave. After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its current-source pull-up circuit. The active master re-enables its current source again when all devices have released and the SCLH signal reaches a HIGH level. The rising of the SCLH is done by a resistor pull-up and so slower, the last part of the SCLH rise time is speeded up because the current-source is enabled. Data transfer only switches back to Fast-mode after a STOP condition (P). A write sequence after the Hs-mode is selected is given in Fig.29. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. After acknowledgement of a write (W) cycle, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines CO and D/C, plus a data byte (see Fig.31 and Table 4). The last control byte is tagged with a cleared most significant bit, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus.
The PCF8813 is a slave receiver/transmitter. If data is to be read from the device the SDAH pad must be connected, otherwise SDAHOUT may be unused. Hs-mode can only commence after the following conditions: * START condition (S) * 8-bit master code (00001XXX) * Not-acknowledge bit (A). The master code has two functions, as shown in Figs 29 and 30, it allows arbitration and synchronization between competing masters at Fast-mode speeds, resulting in one winner. Also the master code indicates the beginning of an Hs-mode transfer. As no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge (A). After this A-bit, and the SCLH line has been pulled up to a HIGH level, the active master switches to Hs-mode and enables at tH the current-source pull-up circuit for the SCLH signal (see Fig.30). The active master will then send a repeated START condition (Sr) followed by a 7-bit slave address with a R/W-bit, and receives an acknowledge bit (A) from the Table 4 BIT CO CO and D/C definition 0/1 0 1 D/C 0 1 0 1 0 1 R/W N/A
ACTION last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or RE-START condition another control byte will follow the data byte unless a STOP or RE-START condition is received data byte will be decoded and used to set-up the device data byte will return the status byte data byte will be stored in the display RAM RAM read back is not supported condition (P) and switches back to Fast-mode, however, to reduce the overhead of the master code, its possible that a master links a number of Hs-mode transfers, separated by repeated START conditions (Sr). A read sequence (see Fig.32) follows after the Hs-mode is selected. The PCF8813 will immediately start to output the requested data until a NOT acknowledge is transmitted by the master. Before the read access, the user has to set the D/C-bit to the appropriate value by a preceding write access. The write access should be terminated by a RE-START condition so that the HS-mode is not disabled.
After the last control byte, depending on the D/C bit setting, a series of display data bytes or command data bytes may follow. If the D/C-bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is updated automatically and the data is directed to the intended PCF8813. If the D/C-bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8813. At the end of the transmission the I2C-bus master issues a STOP
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
,,,,,,,,,, ,,,,,,,,,,
F/S-mode S MASTER CODE A Sr SLAVE ADD. R/W A
Hs-mode (current-source for SCLH enabled)
DATA (n bytes + ack.)
,, ,, ,,,, ,,,,
F/S-mode A/A P Hs-mode continues Sr SLAVE ADD.
MSC616
Fig.29 Data transfer format in Hs-mode.
S SDAH
8-bit Master code 00001xxx
A
t1 tH
SCLH
1
2 to 5
6
7
8
9
Fs mode
Sr
7-bit SLA
R/W
A
n x (8-bit DATA
+
A/A)
Sr P
SDAH
SCLH
1
2 to 5
6
7
8
9
1 Hs-mode
2 to 5
6
7
8
9 If P then Fs mode If Sr (dotted lines) then Hs mode
tH = MCS current source pull-up = Rp resistor pull-up
tFS
MSC618
Fig.30 Complete data transfer in Hs-mode.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
acknowledge from PCF8813
acknowledge from PCF8813
acknowledge from PCF8813
acknowledge from PCF8813
acknowledge from PCF8813
SS Sr 0 1 1 1 1 A A 0 A 1 D/C 10 slave address
control byte
A
data byte
A 0 D/C
control byte
A
data byte n 0 bytes MSB . . . . . . . . . . . LSB
AP
R/W CO
2n 0 bytes
CO
1 byte
MGU634
Fig.31 Master transmits in Hs-mode to slave receiver; write mode.
handbook, full pagewidth
acknowledgement from PCF8813 SS Sr 0 1 1 1 1 A A 1 A 10 slave address R/W
NOT acknowledgement from Master
status information
AP
STOP condition
MGU635
Fig.32 Master receives from slave transmitter (status register is read); read mode.
10.3
Command decoder
The command decoder identifies command words that arrive on the I2C-bus. * Pairs of bytes - first byte determines whether information is display or instruction data - second byte contains information. * Stream of information bytes after CO = 0; display or instruction data depending on last D/C-bit.
The most significant bit of a control byte is the continuation bit CO. If this bit is logic 1, it indicates that only one data byte, either command or RAM data, will follow. If the bit is logic 0, it indicates that a series of data bytes, either command or RAM data, may follow. The DB6 bit of a control byte is the RAM data/command bit D/C. When this bit is logic 1, it indicates that a RAM data byte will be transferred next. If the bit is at logic 0, it indicates that a command byte will be transferred next.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
11 INSTRUCTIONS The PCF8813 interfaces via the 8-bit parallel interface, two different 3-line serial interfaces, 4-wire serial interface or an I2C-bus interface. Processing of the instructions does not require the display clock. In the case of the parallel and 4-wire serial interface, data accesses to the PCF8813 can be divided into two areas; those that define the operating mode of the device, and those that fill the display RAM; the distinction being the D/C input. When the D/C input is set to logic 0, the chip will respond to instructions as defined in Table 5. When the D/C bit is at logic 1, the chip will send data into the RAM. When the 3-wire serial interface or the I2C-bus interface is used, the distinction between instructions that define the
PCF8813
operating mode of the device and those that fill the display RAM is made respectively by the display data length instruction (4-line SPI) or by D/C bit in the data stream (3-line serial interface and I2C-bus interface). There are four types of instructions: * Defining PCF8813 functions such as display configuration, etc. * Setting internal RAM addresses * Performing data transfer with internal RAM * Other instructions. In normal use, category 3 instructions are used most frequently. To lessen the MPU program load, automatic incrementing by one of the internal RAM address pointers after each data write is implemented.
Table 5 Instruction set Instructions not expressly defined in this table and reserved instructions are not allowed in PCF8813 applications. COMMAND BYTE INSTRUCTION D/C R/W DB7 (MSB) DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) DESCRIPTION
H = 0 or 1 NOP Function set 0 0 0 0 0 0 0 0 0 1 0 MX 0 MY 0 PD 0 V 0 H no operation Power-down control; entry mode read status byte for serial and I2C-bus interfaces reads parallel interface status byte writes data to RAM
Read status byte
0
1
0
0
0
1
1
0
(1)
(1)
Read status byte
0
1
BUSY
DON
RES
MF2
MF1
MF0
DS1
DS0
Write data H=0 Reserved Display control Set lower/higher program range Set power control HVgen on/off Display configuration
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 1 1 1 0
0 1 0 0 0 0
1 D 0 0 1 D0
X 0 0 1 1 0
X E PRS PC (1) BRS
do not use sets display configuration VLCD programming range switch HVgen on/off double command byte: set data order; top/bottom row swap mode
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
COMMAND BYTE INSTRUCTION Set display data length D/C R/W 0 0 0 0 DB7 (MSB) 0 0 DB6 1 D6 DB5 1 D5 DB4 1 D4 DB3 (1) D3 DB2 (1) D2 DB1 (1) D1 DB0 (LSB) (1) D0 DESCRIPTION double command byte; set display data length, only used in 3-line SPI sets Y address of RAM: 0 Y 9
Set Y address of RAM Set maximum Y address Set maximum X address Set X address of RAM H=1 Reserved Reserved Temperature compensation Set HVgen stages Bias system Reserved Normal or partial display mode
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 1
1 1 0 1
0 0 0 1
0 1 0 0
Y3 (1)
Y2 (1)
Y1 (1)
Y0 (1)
Ymax3 Ymax2 Ymax1 (1) (1) (1)
double command Ymax0 byte: set maximum Y: 0 Y 8 (1) Xmax0 X0 double command byte: set maximum X: 0 Y 101 sets X address of RAM: 0 X 101
Xmax6 Xmax5 Xmax4 Xmax3 Xmax2 Xmax1 X6 X5 X4 X3 X2 X1
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 1 0
0 0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 1 0
0 0 0 1 0 0 (1) 0 0
0 0 1 0 BS2 (1) (1) (1) 0
0 1 TC1 S1 BS1 (1) (1) (1) 0
1 X TC0 S0 BS0 (1) (1) (1) N/P set temperature coefficient (TCx) set multiplication factor set bias system (BSx) double command byte: do not use double command byte: set normal or partial display mode double command byte: set mask register for FPMR mode (1 : 9, 17, and 25 to 64) double command byte: set start row 0 X 66 double command byte; sets RAM line address to be displayed 0 L 66
Free programmable MUX rate
0 0
0 0
0 M7
1 M6
1 M5
0 M4
1 M3
(1) M2
(1) M1
(1) M0
Set initial row to be displayed Set RAM line address for initial row
0 0 0 0
0 0 0 0
0 0 0 0
1 C6 1 L6
0 C5 0 L5
0 C4 1 L4
1 C3 1 L3
(1) C2 (1) L2
(1) C1 (1) L1
(1) C0 (1) L0
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
COMMAND BYTE INSTRUCTION Disable OTP circuitry Enter module maker calibration mode Software reset Set VPR Note 1. = don't care. Table 6 BIT PD H V PC MX MY TRS BRS DO PRS N/P C[6:0] L[6:0] Ymax[3:0] Xmax[6:0] D, E TC[1:0] S[1:0] BS[2:0] VPR[6:0] M[7:0] chip active basic command set horizontal addressing power control off normal X addressing display is not vertically mirrored top rows are not mirrored bottom rows are not mirrored LSB is on top VLCD programming range LOW partial display driving mode Explanation of mnemonics used in Table 5 0 1 chip is in Power-down mode extended command set vertical addressing power control on X address is mirrored display is vertically mirrored top rows are mirrored bottom rows are mirrored MSB is on top VLCD programming range HIGH normal display driving mode RESET STATE 1 0 0 1 0 0 0 0 1 0 1 0000000 0000000 1000 1100101 00 00 00 000 0000000 11111111 D/C R/W 0 0 0 0 0 0 0 0 DB7 (MSB) 0 0 0 1 DB6 0 0 1 VPR6 DB5 0 0 1 VPR5 DB4 1 1 1 VPR4 DB3 1 1 0 VPR3 DB2 1 1 0 VPR2 DB1 0 1 0 VPR1 DB0 (LSB) 0 0 1 VPR0 DESCRIPTION disable OTP circuitry module maker calibration enable software reset write VPR to register
sets the initial R0 of the display.; this command cannot access R67 (icon row) sets the line address of the display RAM to be displayed on the initial R0; this command cannot access R67 sets maximum Y address for wraparound sets the maximum X address display control; see Table 8 set temperature coefficient; see Table 9 set voltage multiplication factor; see Table 10 bias system VLCD programming set partial display (full display = 11111111)
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
Table 7 BIT BUSY DON RES MF[2:0] DS[1:0] Table 8 D 0 1 0 1 Table 9 TC1 0 0 1 1 0 = display OFF; 1 = display ON 0 = reset NOT in progress; 1 = reset in progress manufacturer identification bits Read status byte FUNCTION 0 = chip is able to accept new commands; 1 = chip is unable to accept new commands
PCF8813
device recognition; currently has a fixed value of 00 (recognition bits for a driver with 64 to 67 rows) Display control; bits D and E E 0 0 1 1 display blank normal mode all display segments on inverse video mode FUNCTION 11.2 Reset function
After reset the LCD driver has the following state: * Power-down mode (PD = 1) * Horizontal addressing (V = 0) * Normal instruction set (H = 0) * Display blank (D and E = 00) * Address counter X[6:0] = 0000000 and Y[3:0] = 0000 * Temperature control mode TC[1:0] = 00 * VLCD is equal to 0 and PRS = 0 * Power control is enabled (PC = 1) * Normal row driving of display (N/P = 1) * Partial mode set for all rows available (M[7:0] = 11111111) * HV generator programmed off (VPR[6:0] = 0000000) * 2 x voltage multiplier (S[1:0] = 00) * After power-on, RAM data is undefined, the reset signal does not change the content of the RAM * Data order DO = 0 * All LCD outputs at VSS (display off) * Bias system (BS[2:0] = 000 * Display start line set to R0 (C[6:0] = 000000) * RAM line address set to 0 (L[6:0] = 000000) * Maximum X address = 101 (Xmax[6:0] = 1100101) * Maximum Y address = 8 (Ymax[3:0] = 1000) * Display is not mirrored (MX = 0; MY = 0 and BRS = 0). 11.3 Power-down mode
Set temperature coefficient; bits TC[1:0] TC0 0 1 0 1 FUNCTION VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3
Table 10 Set voltage multiplication factor; bits S[1:0] S1 0 0 1 1 11.1 S0 0 1 0 1 FUNCTION 2 x voltage multiplier 3 x voltage multiplier 4 x voltage multiplier 5 x voltage multiplier
Initialization
Immediately following Power-on, all internal registers as well as the RAM content are undefined. A RES pulse must be applied to the reset input. Reset is accomplished by applying an external reset pulse (active LOW) at the pad RES. When reset occurs within the specified time all internal registers are reset, however the RAM is still undefined. The RES input must be 0.3VDD when VDD reaches VDD(min) (or higher) within a maximum time tVHRL after VDD going HIGH (see Fig.37). A reset can also be made by sending a reset command. This command can be used during normal operating but not to initialize the chip after Power-on.
Power-down mode gives the following circuit status: * VLCD discharges to VSS as Power-down mode occurs * All LCD outputs go to VSS (display off) * Bias generator and VLCD generator switch-off, VLCD can be disconnected * Oscillator switches off (external clock is possible) * RAM contents are not cleared; RAM data can be written.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
11.4 Display Control 11.7
PCF8813
Set maximum X address or Y address
Bits D and E (see Table 8) select the display mode. When bit MX = 0, the display RAM is written from left to right (X = 0 is on the left side and X = 101 is on the right side of the display). When bit MX = 1, the display RAM is written from right to left (X = 0 is on the right side and X = 101 is on the left side of the display). The bit MX has an impact on the way the RAM is written. So if horizontal mirroring of the display is required, the RAM must first be rewritten. When bit MY = 1, the display is mirrored vertically. A change of bit MY has an immediate effect on the display. When bit V = 0, horizontal addressing is selected and data is written into the DDRAM as shown in Fig.5. When bit V = 1, vertical addressing is selected, then data is written into the DDRAM as shown in Fig.6. 11.5 Set Y address of RAM
These two commands (Xmax[6:0] and Ymax[3:0]) set the maximum address for wraparound to occur for the columns. The range of Xmax is 0 to 101. The maximum Y address also sets the Y address for wraparound to occur. The range of Ymax is 0 to 8. By design, the maximum Y setting cannot access bank 10. Xmax and Ymax together also define when wraparound-to-zero takes place. These two commands are effective only when writing to the RAM. 11.8 Set display start line, initial start row and row 0
Bits Y[3:0] define the Y address vector address of the display RAM. Table 11 Range of Y address and allowable X range Y ADDRESS RAM CONTENT 3 0 0 0 0 0 0 0 0 1 1 2 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 0 bank 0 (display RAM) bank 1 (display RAM) bank 2 (display RAM) bank 3 (display RAM) bank 4 (display RAM) bank 5 (display RAM) bank 6 (display RAM) bank 7 (display RAM) bank 8 (display RAM) bank 10 (display RAM) ALLOWED X RANGE 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101
Set display start line L[6:0] allows the display line address of the display RAM to be chosen. The range is from line 0 to line 66 inclusive. The RAM address line 67 is not available for this command as it is reserved for icons. This command has an effect on the mapping between the data of the RAM and the display. The L address specifies which rows of the RAM are output to which row outputs of the display. The value of the L address defines which row of the RAM will be row 0. Row 0 of the display can in turn be set by the set initial row command C[6:0]. Figure 33 shows an example of how RAM data is mapped onto the display. In this example, the L command sets the data on line 8 of the RAM to be displayed. This data is displayed on a row set by the C command (16). When L and C are set to 8 and 16 respectively, data from RAM lines 4 to 7 is displayed on display rows 12 to 15 and RAM data from lines 15 to 18 is displayed on display lines 23 to 26. When MY is active (MY = 1), the data from Fig.33 is mapped from the RAM to the display as shown in Fig.34. Note the `new' location of C after MY. 11.9 Set normal or partial display mode
In bank 8 only three bits are accessed, and in bank 10 only one bit is accessed. 11.6 Set X address of RAM
When N/P = 1, the PCF8813 can operate only as a 67 + 1 row driver operating with a 1 : 68 multiplex rate. When N/P = 0, the driver is used in free programmable multiplex rate where up to eight different multiplex rates can be selected in steps of 8, depending on the mask register value M[7:0]. When the PCF8813 is operating in FPMR mode, only the first 64 rows plus the icon row are available to the user. Table 12 Normal or partial mode display N/P 0 1 ACTION partial mode display: 65 rows available normal mode display: 68 rows available
The X address points to the columns. The range of X is 0 to 101 (65H).
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
11.10 Free programmable multiplex rate The free programmable multiplex rate concept allows the user to limit the number of rows selected to groups of eight. Any, or all of these groups of rows can be enabled or disabled. The mask register command (M[7:0]) allows the user to turn-on or turn-off blocks of eight rows. Each mask value controls a block of eight rows, thus in partial mode the maximum number of rows available is 64 plus the icon row. A logic 1 in the mask register enables the rows available within that block of rows, and a logic 0 disables them. The mask register causes the row counter to count eight bits and then jump to the next enabled 8-bit group. For example, if the mask register value is 00001101, then the rows available will be 0 to 7, 16 to 23, 24 to 31 and 67.
PCF8813
Rows 8 to 15 and 32 to 63 have been skipped. This information is also mapped to the RAM so that only the contents of active rows are displayed. Table 13 Range of free programmable multiplex rates MASK REGISTER M0 M1 M2 M3 M4 M5 M6 M7 ROWS AVAILABLE R0 to R7 + icon row R8 to R15 + icon row R16 to R23 + icon row R24 to R31 + icon row R32 to R39 + icon row R40 to R47 + icon row R48 to R55 + icon row R56 to R63 + icon row
Table 14 Examples of display normal driving mode and partial display driving mode MASK REGISTER MASK VALUE ROW SEQUENCE NORMAL DISPLAY
N/P = 1 (the mask value is don't care when N/P = 1 because all rows are enabled) M0 M1 M2 M3 M4 M5 M6 M7 1 0 0 1 0 0 0 1 0 to 7 8 to 15 16 to 23 24 to 31 32 to 39 40 to 47 48 to 55 56 to 63 64 to 66 67 (icon row) keyboard locked battery status: XXX address book connection time network: YYY reception strength 2 June; 15:25
not available in mask register not available in mask register N/P = 0 M0 M1 M2 M3 M4 M5 M6 M7 1 0 0 1 0 0 0 1
0 to 7 8 to 15 16 to 23 24 to 31 32 to 39 40 to 47 48 to 55 56 to 63 67 (icon row)
battery status: XXX
network: YYY
keyboard locked
not available in mask register
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
set initial display line and start row when MY = 0 RAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31 ROW 32 ROW 33 ROW 34 ROW 35 ROW 36 ROW 37 ROW 38 ROW 39
Y address
Display
0
L-address = 8
1
C-address = 16
2
3
7
8 9
icons only
56 57 58 59 60 61 62 63 64 65 66 67
ROW 64 ROW 65 ROW 66 ROW 67
icons only
MGU636
Fig.33 Effect of L address when MY = 0.
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34
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
set initial display line and start row when MY = 1 RAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ROW 0 ROW 1 ROW 2 ROW 3
Y address
Display
0
L-address = 8
1
2
3
effective C-address
7
8 9
icons only
56 57 58 59 60 61 62 63 64 65 66 67
ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 41 ROW 42 ROW 43 ROW 44 ROW 45 ROW 46 ROW 47 ROW 48 ROW 49 ROW 50 ROW 51 ROW 52 ROW 53 ROW 54 ROW 55 ROW 56 ROW 57 ROW 58 ROW 59 ROW 60 ROW 61 ROW 62 ROW 63 ROW 64 ROW 65 ROW 66 ROW 67
icons only
MGU637
Fig.34 Effect of L address when MY = 1.
2004 Mar 05
35
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
11.11 Set HV generator stages The PCF8813 incorporates a software-configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 2 x VDD2. Other voltage multiplier factors are set via the set HVgen stages command bits S[1:0]. 11.12 Bias system The bias voltage levels are set in the ratio of R - R - nR - R - R giving a 1/(n + 4) bias system. Different multiplex rates require different n factors. This is programmed by BS[2:0] (see Table 15). For multiplex rates of 1 : 68 the optimum bias value n is given by: n = 68 - 3 = 5.246 = 5 resulting in 1/9 bias. V5(2) V6 Notes Table 16 LCD bias voltage SYMBOL V1 V2 V3 V4(1) BIAS VOLTAGES VLCD (n + 3) ----------------(n + 4) (n + 2) ----------------(n + 4) 2 ----------------(n + 4) 1 ----------------(n + 4) VSS
PCF8813
BIAS VOLTAGES FOR 1/9 BIAS VLCD
8/ 9
x VLCD x VLCD x VLCD x VLCD
7/
9
2/
9
1/
9
Changing the bias system from the optimum value will have a consequence for the contrast and viewing angle. One reason to depart from the optimum would be to reduce the required operating voltage. A compromise between contrast and operating voltage must be found for any particular application. Table 15 Bias system programming BS[2] BS[1] BS[0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0 RECOMMENDED MULTIPLEX RATES 1 : 100 1 : 80 1 : 65 or 1 : 67 1 : 48 1 : 34 or 1 : 40 1 : 24 1 : 18 or 1 : 16 1 : 10, 1 : 9 or 1 : 8
VSS
1. Operation of bias level V4 is given for V4 > VSS + 0.9 V. For higher multiplex rates, VLCD has to be selected accordingly. 2. For multiplex rates equal to or lower than 1 : 24 (n = 2) operation of the bias level V5 is limited to voltages V5 < VDD2,3 - 1.1 V. VLCD has to be selected accordingly.
The operating voltage can be set by software through the interface. The binary number VOP representing the operating voltage can be set according to the following formula: V OP = V CAL [ 4:0 ] + V PR Where: VOP is an 8-bit unsigned number used internally for generation of the LCD supply voltage VLCD VCAL is a 5-bit twos complement number set by the module maker; see Table 17 VPR is an 8-bit unsigned number composed of PRS and VPR* set by an interface command. The corresponding voltage at the reference temperature, TCUT, can be calculated as: V LCD ( Tcut ) = ( a + V OP x b )
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
The generated voltage at VLCD is dependent on the temperature, programmed temperature coefficient (TC) and the programmed voltage at the reference temperature (TCUT): V LCD = [ a + V OP x b ] x [ 1 + TC x ( T - T CUT ) ] TCUT and voltages a and b for each temperature coefficient are quoted in Table 17. The maximum voltage that can be generated is dependent on the voltage of VDD2 and the display load current. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure that while setting the VPR
PCF8813
register and selecting the temperature compensation, under all conditions and including all tolerances the VLCD maximum limit of 9.0 V will never be exceeded. For a particular liquid crystal, the optimum VLCD can be calculated for a given multiplex rate. For 1 : 68, the optimum operating voltage of the liquid crystal can be calculated as; 1 + 68 V LCD = -------------------------------------- x V th = 6.98 x V th 1 2 x 1 - ---------- 68 where Vth is the threshold voltage of the liquid crystal used.
Table 17 Parameters of HV generator programming (typical values) Nominal temperature = 27 C; temperature coefficients calculated at nominal VLCD = 8.6 V. SYMBOL a b TCUT TC PARAMETER first level VLCD voltage programmed voltage step reference temperature temperature coefficient TC0 4.57 30.5 27 0.00 TC1 4.27 28.5 27 -0.25 TC2 4.01 26.7 27 -0.48 TC3 3.84 25.6 27 -0.64 V mV C mV/K UNIT
handbook, full pagewidth
MGT847
V LCD
b
a
00
01
02
03
04
05
06
...
...
FD
FE
FF
V OP
If VPR[6:0] is set to zero, the charge pump is turned off. Depending on VPR restrictions defined in Table 17 and depending on VCAL, not all VOP[7:0] values can be selected.
Fig.35 VLCD as a function of VOP[7:0] programming.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
12 TEMPERATURE COMPENSATION
PCF8813
Due to the temperature dependency of the liquid crystal viscosity, the LCD controlling voltage VLCD must be increased at lower temperatures to maintain optimum contrast. Figure 36 shows VLCD for high multiplex rates. In the PCF8813 the temperature coefficient to be applied to VLCD can be selected from four values by setting bits TC[1:0].
handbook, full pagewidth
MGT848
VLCD
T
Fig.36 VLCD as a function of liquid crystal temperature.
13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); see notes 1 and 2 SYMBOL VDD1 VDD2, VDD3 VLCD VI ISS II, IO Ptot PO Tstg Tj Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified; all voltages are with respect to VSS unless otherwise specified. 3. VDD2 and VDD3 are always equal. 14 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices"). supply voltage supply voltage (voltage multiplier); see note 3 LCD supply voltage input voltage (any pad) ground supply current DC input or output current total power dissipation power dissipation per output storage temperature junction temperature PARAMETER MIN. -0.5 -0.5 -0.5 -0.5 -50 -10 - - -65 - MAX. +6.5 +4.5 +9.0 VDD + 0.5 +50 +10 300 30 +150 150 V V V V mA mA mW mW C C UNIT
2004 Mar 05
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
15 DC CHARACTERISTICS VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL VDD1 VDD2, VDD3 VLCDIN VLCDOUT VLCD(tol) IDD(tot) IDD1 ILCD VOL VOH VIL VIH IL Rcol Rrow Vcol(tol) Vrow(tol) TC PARAMETER supply voltage (logic circuits) supply voltage (voltage multiplier) LCD supply voltage input generated LCD supply voltage tolerance of generated LCD supply voltage total supply current (IDD1 + IDD2 + IDD3) supply current LCD supply current note 2 note 3 note 1 CONDITIONS MIN. 1.7 2.4 3.0 4.5 -70 - - - - - 100 0.5 10 30 - - - - - 5 5 0 0 TYP.
PCF8813
MAX. 3.3 4.5 9.0 9.0 +70 300 10 35 - 0.2VDD VDD 0.2VDD VDD +1
UNIT V V V V mV A A A A V V V V A k k mV mV
normal mode; notes 4, 5, 6 - Power-down mode; note 7 - external VLCD; notes 4, 6, 8 - external VLCD; notes 4, 6, 8 - IOL = 0.5 mA IOH = -0.5 mA VSS 0.8VDD VSS 0.8VDD VI = VDD or VSS VLCD = 7.6 V; note 9 VLCD = 7.6 V; note 9 note 9 note 9 -1 - - -100 -100
Logic circuits LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage leakage current
Column and row outputs column output resistance C0 to C101 row output resistance R0 to R67 bias tolerance C0 to C101 bias tolerance R0 to R67 20 20 +100 +100
LCD supply voltage generator VLCD temperature compensation temperature coefficient 0 temperature coefficient 1 temperature coefficient 2 temperature coefficient 3 Notes 1. VDD2 and VDD3 are always equal. 2. The maximum possible VLCD voltage that may be generated depends on voltage, temperature and load (display). 3. Valid for the temperature, VPR and TC values used at calibration. 4. Normal mode and internal clock. 5. Conditions: VDD1 = 1.8 V; VDD2 = 2.70 V; VLCD = 7.6 V; voltage multiplier = 4 x VDD2; bias system 1/9; inputs at VDD1 or VSS; VLCD generation = internal; VLCD output loaded by 10 A; Tamb = 25 C. 6. fINTCLK = 0 (no data bus clock). 7. Power-down mode; during Power-down all static currents are switched off. VLCD(nom) = 8.6 V - - - - 0.00 -0.23 -0.48 -0.64 - - - - mV/K mV/K mV/K mV/K
2004 Mar 05
39
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
8. VLCD external voltage applied to VLCDIN and VLCDSENSE inputs; VLCDOUT disconnected; VPR and PC set to 0 (charge pump off); display load current is not transmitted to IDD. 9. Load current = 10 A; outputs tested one at a time. 16 AC CHARACTERISTICS VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = -40 to +85 C; all timings specified are based on 20% to 80% of VDD with an input voltage swing of VSS to VDD; unless otherwise specified. SYMBOL fext fframe PARAMETER external clock frequency frame frequency CONDITIONS note 1 internal oscillator note 2 note 3 tVHRL tRW tR(oper) VDD on to RES LOW time reset pulse width LOW time end of reset pulse to interface operational see Fig.37 see Fig.37 see Fig.37 56 62 0(4) 500 1000 66 69 - - - 76 76 1 - - Hz Hz s ns ns MIN. 20 TYP. 38 MAX. 65 UNIT kHz
6800-type parallel bus; VDD1 = 1.8 to 3.3 V; see Figs 38 and 39 tDCSU tDCHD TDS(cyc) tDSL tDSH tRWSU tRWHD tESU tEHD tDATSU tDATHD tDATACC tDATOH data/command set-up time data/command hold time data strobe cycle time data strobe LOW time data strobe HIGH time read/write set-up time read/write hold time chip enable set-up time chip enable hold time data set-up time data hold time output access time output disable time 0 0 1000 300 300 0 0 0 0 80 30 - 10 - - - - - - - - - - - - - - - - - - - - - - - - 25 - - - - - - - - - - 280 200 ns ns ns ns ns ns ns ns ns ns ns ns ns
8080-type parallel bus; VDD1 = 1.8 to 3.3 V; see Fig.40 tDCSU tDCHD TDS(cyc) tDSLR tDSLW tDSHR tDSHW tDATSU tDATHD tDATACC tDATOH 2004 Mar 05 data/command set-up time data/command hold time data strobe cycle time data strobe LOW time (read) data strobe LOW time (write) data strobe HIGH time (read) data strobe HIGH time (write) data set-up time data hold time output access time output disable time 40 0 0 1000 120 240 120 120 80 30 - 10 25 - - - - - - - - 280 200 ns ns ns ns ns ns ns ns ns ns ns
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
SYMBOL
PARAMETER
CONDITIONS -
MIN. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TYP.
MAX.
UNIT
3-line and 4-line SPI and serial interface; VDD1 = 1.8 to 3.3 V; Figs 41 to 44; note 5 fSCLK Tcyc tPWH1 tPWL1 tPWH2 tS1 tH1 tS2 tH2 tS3 tH3 t1 t2 t3 t4 Cb Rb SCLK frequency SCLK cycle time SCLK pulse width HIGH SCLK pulse width LOW SCE minimum HIGH time SDATA set-up time SDATA hold time SCE set-up time SCE hold time data/command set-up time data/command hold time SDOUT access time SDOUT disable time SCE hold time SDOUT disable time capacitive load for SDOUT series resistance for SDOUT note 7 note 8 note 8 note 6 9 - - - - - - - - - - 80 80 - 80 30 500 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF 111 45 45 50 50 50 60 45 50 50 - - 50 - - -
I2C-bus interface in Fast-mode; VDD1 = 1.7 to 3.3 V; Fig.45 fSCL tLOW tHIGH tSU;DAT tHD;DAT cb tSU;STA tHD;STA tSU;STO tSP I2C-bus fSCLH tSU;STA tHD;STA tLOW tHIGH tSU;DAT SCL clock frequency SCL clock low period SCL clock high period data set-up time data hold time capacitive load represented by each bus line set-up time for a repeated START condition START condition hold time set-up time for STOP condition tolerable spike width on bus note 9 0 1.3 0.6 100 0 - 0.6 0.6 0.6 - 400 - - - 0.9 400 - - - 50 kHz s s ns s pF s s s ns
interface in Hs-mode; VDD1 = 1.7 to 3.3 V; Fig.46 SCLH clock frequency set-up time (repeated) START condition hold time (repeated) START condition LOW period of the SCLH clock HIGH period of the SCLH clock data set-up time 0 160 160 160 60 10 3.4 - - - - - MHz ns ns ns ns ns
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
SYMBOL tHD;DAT tSU;STO Cb
PARAMETER data hold time set-up time for STOP condition capacitive load for SDAH and SCLH lines capacitive load for SDAH + SDA line and SCLH + SCL line
CONDITIONS 0
MIN. - - - - - 160
TYP. -
MAX. 70 100 400 5
UNIT ns ns pF pF ns
total capacitance of one bus line
- -
tSP Notes
tolerable spike width on bus
note 9
-
f ext 1. fframe = ------- : (n depends on the multiplex rate, see Table 18). n 2. VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = -40 to +85 C, all MUX settings. 3. VDD1 = 2.4 V to 3.0 V; Tamb = -20 C to +70 C; MUX = 68. 4. RES may be LOW before VDD on. 5. Maximum values are for fSCLK = 9 MHz. Series resistance includes ITO track + connector resistance + printed-circuit board. 6. SDOUT disable time for SPI 3-line or 4-line interface. 7. SDOUT disable time for serial 3-line interface. 8. Typical conditions: VDD1 = 2.8 V, Tamb = 20 C, MUX = 68; fframe = 70 3.4 Hz. 9. Inputs SDAH and SCLH are filtered and will reject spikes on the bus lines with a width of less than tSW(max). Table 18 Value of n as a function of multiplex rate MULTIPLEX RATE 68 65 57 49 41 33 25 17 9 n 483 462 464 500 504 476 468 505 500
2004 Mar 05
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
VDD1 t VHRL RES t R(oper) SCE
MGU285
t RW
Fig.37 Reset timing.
handbook, full pagewidth
D/C t DCSU T DS(cyc) t DSL E t RWHD t DSH t DCHD
t RWSU R/W
t ESU SCE t DATSU D0 to D7 (write) t DATACC D0 to D7 (read)
t EHD
t DATHD
t DATOH
MGU638
Fig.38 Parallel interface timing (6800-type) with clocking performed by enable input (E).
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43
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
D/C t DCSU E t RWSU t RWHD t DCHD
R/W
TDS(cyc) t DSL t DSH
SCE t DATSU t DATHD
D0 to D7 (write) t DATACC D0 to D7 (read)
MGU639
t DATOH
Fig.39 Parallel interface timing (6800-type) with clocking performed by chip select input (SCE).
2004 Mar 05
44
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
D/C t DCSU T DS(cyc) t DSLR, t DSLW WR, RD t DSHR, t DSHW t DCHD
SCE t DATSU D0 to D7 (write) t DATACC D0 to D7 (read)
MGU640
t DATHD
t DATOH
Fig.40 Parallel interface timing (8080-type).
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45
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
t S2
t H2
t PWH2
SCE t S2 t PWL1 SCLK t PWH1 T cyc
t S1 SDATA
t H1
MGU642
Fig.41 3-line serial interface timing.
handbook, full pagewidth
t S2
t H2
t PWH2
SCE t S3 D/C t S2 t PWL1 SCLK t PWH1 T cyc t H3
SDATA
MGU854
Fig.42 4-line serial interface timing.
2004 Mar 05
46
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
SCE t3 SCLK t H1 SDATA t S1
t1 SDOUT
t2
MGW759
Fig.43 3-line and 4-line serial peripheral (SPI) interface timing (read mode).
handbook, full pagewidth
SCE t3 SCLK t H1 SDATA t S1
t1 SDOUT
t4
MGW760
Fig.44 3-line serial interface timing (read mode).
2004 Mar 05
47
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
SDA tf
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL tHD;STA tSU;STA tSU;STO
S
tHD;DAT
tHIGH
Sr
P
S
MSC610
Fig.45 I2C-bus timing diagram (Fast-mode).
handbook, full pagewidth
Sr tfDA
trDA
Sr
P
SDAH
tSU;STA
tHD;DAT tHD;STA tSU;DAT
tSU;STO
SCLH tfCL trCL1
(1)
trCL tHIGH tLOW tLOW tHIGH
trCL1
(1)
MGK871
= MCS current source pull-up = Rp resistor pull-up
(1) Rising edge of the first SCLH clock pulse after an acknowledge bit.
Fig.46 I2C-bus timing diagram (Hs-mode).
2004 Mar 05
48
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
17 MODULE MAKER PROGRAMMING One Time Programmable (OTP) technology has been implemented on the PCF8813. This enables the module maker to program some features of the PCF8813 after it has been assembled on an LCD module. Programming is made under the control of the interfaces and using the special pad VOTPPROG. This pad must be made available on the module glass but does not need to be accessed by the set maker. Module maker programming is an extension of the normal functions of the PCF8813 and is effective until specifically instructed otherwise with the disable OTP command. The PCF8813 features three module maker programmable parameters: * VLCD calibration (5 bits) * Manufacturer identity (3 bits) * Seal bit (1-bit). 17.1 LCD voltage calibration
PCF8813
Referring to Fig.47, the VLCD calibration parameter comprises a 5-bit code (VCAL[4:0]). The code is implemented in twos complement notation giving a positive or negative offset to the VPR register. The range of the VPR[6:0] register is 0 to 127. The adder in the circuit takes this into account by having underflow and overflow protection added to it. In the event of an overflow, the output will be clamped to 255, and in the case of an underflow the output will be clamped to 0. Given that V OP = V CAL + V PR and V LCD = a + V OP x b
T(norm)
VLCD can be calculated using parameters a and b that are defined in Table 17. An example of the relationship between VCAL code and the VLCD calibration is shown in Table 19, where b is assumed to be 25.6 mV. Possible values for VCAL are given in Table 19. The default value for VCAL when OTP is disabled is VCAL[4:0] = 00000.
handbook, full pagewidth
VLCD calibration: 5-bit SIGNED value VCAL[4:0]
-16 to +15
+
VPR register: 7-bit UNSIGNED value VPR [6:0] 0 to +127
VOP
to high voltage generator
MGU644
Fig.47 VLCD calibration.
2004 Mar 05
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
Table 19 VCAL codes and associated nominal calibration voltage when the temperature coefficient is set to TC3 VCAL +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 VCAL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 VLCD CALIBRATION (mV) 0 (default) +25.6 +51.2 +76.8 +102.4 +128.0 +153.6 +179.2 +204.8 +230.4 +256.0 +281.6 +307.2 +332.8 +358.4 +384.0 -25.6 -51.2 -76.8 -102.4 -128.0 -153.6 -179.2 -204.8 -230.4 -256.0 -281.6 -307.2 -332.8 -358.4 -384.0 -409.6 17.4 17.4.1 One time programming ARCHITECTURE Table 20 Seal bit definition SEAL BIT 0 1 17.2 Manufacturer identity
PCF8813
The second OTP feature defines the manufacturer identity. A 3-bit code MF[2:0] is used to define this parameter. The default manufacturer identity is MF[2:0] = 000. 17.3 Seal bit
Module maker programming is performed in a special mode; the calibration mode MM. This mode is entered via the interface command, MM. To prevent wrongful programming, a seal bit prevents the device from entering the calibration mode. This seal bit, once programmed, cannot be reversed, thus further changes in programmed values are not possible. However it is possible to disable all programmed values by applying the disable OTP command. Applying the programming voltages when not in MM mode will have no effect on the programmed values.
ACTION possible to enter calibration mode calibration mode disabled
The OTP circuitry in the PCF8813 contains nine bits of data: five for VLCD calibration, three for the manufacturer identity and one for the seal bit. The circuitry for 1-bit is called an OTP slice. Each OTP slice consists of two main parts: the OTP cell (a non-volatile memory cell) and the shift register cell (a flip-flop). The OTP cells are accessible only through their shift register cells; both reading-from and writing-to the OTP cells are performed with the shift register cells, but only the shift register cells are visible to the rest of the circuit. The basic OTP architecture is shown in Fig.48.
2004 Mar 05
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
DATA TO THE CIRCUIT FOR CONFIGURATION AND CALIBRATION OTP slice
SHIFT REGISTER FLIP-FLOP
SHIFT REGISTER DATA INPUT
SHIFT REGISTER
read data from the OTP cell
write data to the OTP cell
OTP CELLs
MGU289
OTP CELL
Fig.48 Basic OTP architecture.
17.4.2
OPERATIONS
The OTP architecture allows the following operations: * The OTP circuit in the PCF8813 is initialized when a reset is initiated. After the reset initiation, OTP circuits can be disabled only by sending the disable OTP command. * Reading data from the OTP cells. The content of the non-volatile OTP cells is transferred to the shift register where it may affect operation of the PCF8813. * Writing data to the OTP cells. All 9 bits of data are shifted first into the shift register via the serial interface. Then the content of the shift register is transferred to the OTP cells (there are some limitations related to storing data in these cells; see Section 17.6). * Checking calibration without writing to the OTP cells. Shifting data into the shift register allows the effects of the VLCD voltage to be observed. All OTP circuitry of the PCF8813 is enabled until the disable OTP command is given. Once enabled, the reading of data from the OTP cells is initiated by either: * Exit from Power-down mode * The Refresh command (power control). This command works only when the driver is not in Power-down. In both cases, the time required for the reading operation to complete is up to 5 ms. 2004 Mar 05 51
The shifting of data into the shift register is performed in the special mode MM. In the PCF8813, the MM mode is entered through the MM command. Once in the MM mode, the data is shifted into the shift register via any of the interfaces at the rate of 1-bit per command. After transmitting the last (9th) bit and exiting the MM mode, the interface is again in the normal mode and all other commands can be sent. Care should be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the MM mode, otherwise the bits will be in the wrong positions. The value of the seal bit in the shift register is always zero at reset (also applies to all other bits). To make sure the security feature works correctly, the MM command is disabled until a refresh has been made. Once a refresh is completed, the seal bit value in the shift register is valid and permission to enter MM mode can thus be determined. The 9 bits are shifted into the shift register in a predefined order: first 5 bits of VCAL[4:0], followed by 3 bits for MF[2:0] and then the seal bit. The MSB is always first, that is the first bit shifted is VCAL[4] and the seal bit is the last bit.
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
17.5 Interface commands
PCF8813
Instructions additional to those of the instruction set (Table 5) are given in Table 21. Table 21 Additional instructions COMMAND BYTE INSTRUCTION Reset Function set REF (refresh) 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 PC D/C R/W D7 D6 D5 D4 D3 D2 D1 D0 enable OTP circuitry exit Power-down switch HVgen on/off to force refresh of shift register wait 5 ms for refresh to take effect Function set MM 17.5.1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 17.5.3 0 1 REFRESH 1 0 set PD = 1 and H = 1 enter MM mode ACTION
DISABLE OTP COMMAND
This is a special instruction for the PCF8813 which disables all included OTP circuitry. In this case, all OTP-related commands are inactive. VCAL and MF have no effect on VLCD and manufacture identification respectively. Once disabled, the mode can only be enabled via a reset. 17.5.2 MODULE MAKER CALIBRATION
The action of the refresh instruction (REF) is to force the OTP shift register to re-load from the non-volatile OTP cells. This instruction takes up to 5 ms to complete. During this time all other instructions may be sent. In the PCF8813, the refresh instruction is associated with the power control instruction so that the shift register is refreshed automatically every time the high voltage generator is enabled or disabled. However, if this instruction is sent while in Power-down, the PC bits are updated but the refreshing is ignored. 17.6 Filling the shift register
Instruction (MM) enters the device into the calibration mode. This mode enables the shift register for loading and allows programming of the non-volatile OTP cells to take place. If the seal bit is set, then this mode cannot be accessed and the instruction will be ignored. Once in calibration mode all commands are interpreted as shift register data. The mode can only be exited by sending data with bit D7 set to logic 0. Reset will also clear this mode. Each shift register data byte is preceded by D/C = 0 and has only three significant bits, thus the remaining five bits are ignored. Bit D7 is the continuation bit (D7 = 1 indicates remain in MM mode; D7 = 0 indicates exit MM mode). D6 has to be logic 0 until the last bit when the seal bit is set, in which case this is set to logic 1 (D6 is set to logic 1 only when the high voltage used for programming the cells is about to be applied). Bit D0 is the data bit and its value is shifted into the OTP shift register on the falling edge of the SCLK clock.
An example of the sequence of commands and data for filling the shift register is shown in Table 22. This example uses the values VCAL = -4 (11100B), MF = 4 (100B is the Philips identifying code) and the seal bit is 0. It is assumed that the PCF8813 has just been reset. After transmitting the last bit the PCF8813 can exit or remain in MM mode (see Table 22, step 1). When in MM mode, the interface does not recognize commands in the normal sense. After this sequence has been applied, it is possible to observe the impact of the data shifted in. The sequence described is not useful for OTP programming because the number of bits with value = 1 is greater than that allowed for programming (see Section 17.7). Figure 49 shows the shift register after this action.
2004 Mar 05
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
Table 22 Example sequence of shift register filling STEP 1 1 3 0 0 0 0 0 0 0 0 D/C R/W D7 D6 D5 1 0 D4 0 1 D3 0 0 D2 0 0 D1 0 1 D0 0 PC ACTION
PCF8813
reset
reset to enable OTP circuitry exit Power-down (PD = 0) switch HVgen on/off to force refresh of shift register wait 5 ms for refresh to take effect set PD to 1(2) and H to 1 enter MM mode shift-in data; VCAL[4] is first bit(3) VCAL[3] VCAL[2] VCAL[1] VCAL[0] MF[2] MF[1] MF[0] seal bit; remain in MM mode
4 5 6 7 8 9 10 11 12 13 14 Notes
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0
1 0 X X X X X X X X X
0 1 X X X X X X X X X
0 1 X X X X X X X X X
1 1 X X X X X X X X X
0 1 X X X X X X X X X
1 0 1 1 1 0 0 1 0 0 0
1. X = don't care. 2. PD does not have to be set to 1 if the effects of VCAL are intended to be observed on VLCDOUT. 3. Bit data is not in the correct shift register position until all bits have been sent.
handbook, full pagewidth
OTP SHIFT REGISTER shifting direction SEAL BIT = 0
LSB MMMF[2:0] MSB LSB
MMVOPCAL [4:0] 0 1 1
MSB
0
0
1
0
1
MGU645
Fig.49 Shift register contents after example sequence of Table 22.
2004 Mar 05
53
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
17.7 Programming flow
PCF8813
cell at a time is recommended. This is achieved by filling all but one shift register cells with 0. The programming specification refers to the voltages at the chip pads, therefore contact resistance must be considered by the user. An example of the sequence of commands and data for OTP programming is given in Table 23. The order for programming cells is not significant but it is recommended that the seal bit is programmed last. Once the seal bit has been programmed it is not possible to re-enter the MM mode. It is assumed that the PCF8813 has been reset just before the programming commences.
Programming is achieved in MM mode and with application of the programming voltages. Since the data for programming the OTP cell is contained in the corresponding shift register cell, the shift register cell must be loaded with a 1 in order to program the corresponding OTP cell. If the shift register cell contains a 0, then no action will take place when the programming voltages are applied. Once programmed, an OTP cell cannot be de-programmed. Also, a previously programmed cell that is an OTP cell containing a 1 must not be re-programmed. During programming a substantial current flows in the VLCDIN pad. For this reason programming only one OTP Table 23 Example sequence for OTP programming STEP 1 1 3 0 0 0 0 0 0 0 0 1 0 D/C R/W D7 D6 D5 D4 0 1 D3 0 0
D2 0 0
D1 0 1
D0 0 PC
ACTION enable OTP by applying a reset exit Power-down (PD = 0) switch HVgen on/off to force refresh of shift register wait 5 ms for refresh to take effect re-enter Power-down (PD = 1 and H = 1) enter MM mode VCAL[4] (the only bit with value of 1) VCAL[3] VCAL[2] VCAL[1] VCAL[0] MF[2] MF[1] MF[0] seal bit; remain in CALMM mode apply programming voltage at pads VOTPPROG and VLCDIN apply external reset
reset
4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 -
0 0 0 0 0 0 0 0 0 0 0 -
0 0 1 1 1 1 1 1 1 1 1 -
0 0 0 0 0 0 0 0 0 0 1 -
1 0 X X X X X X X X X -
0 1 X X X X X X X X X -
0 1 X X X X X X X X X -
1 1 X X X X X X X X X -
0 1 X X X X X X X X X -
1 0 1 1 1 0 0 0 0 0 0 -
Repeat steps 6 to 15 for each bit that should be programmed to 1 15 Note 1. X = don't care. - - - - - - - - - -
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
17.8 Programming specification
PCF8813
handbook, full pagewidth
tsu(INTCLK)
thd(INTCLK)
INT_CLK
VVOTPPROG
VLCDIN
tsu(gate) tPW
thd(gate)
MGU646
Fig.50 Programming waveforms.
Table 24 Programming parameters SYMBOL VDD1 PARAMETER logic supply voltage VOTPPROG relative to VSS1; note 1 programming active programming inactive VLCDIN voltage applied to pad VLCDIN VLCDIN relative to VSS1; notes 1, 2 programming active programming inactive IOTPPROG ILCDIN Tprog current drawn during programming current drawn during programming ambient temperature during programming 9.0 0 - when programming one bit to logic 1 - 0 1 1 1 1 100 9.50 - 100 850 25 - - - - 120 10.5 VDD2 200 1000 40 - - 10 10 200 V V A A C s s ms ms ms 11.0 0 11.5 - 12.0 VDD1 V V CONDITION MIN. 2.4 TYP. - MAX. UNIT 3.3 V
VOTPPROG voltage applied to pad VOTPPROG
tsu(INTCLK) internal data set-up time after last clock thd(INTCLK) internal data hold time before next clock tsu(gate) thd(gate) tPW Notes VOTPPROG set-up time prior to programming VOTPPROG hold time after programming programming voltage pulse width
1. The voltage drop across the ITO track and zebra connector must be taken into account to guarantee sufficient voltage at the chip pads. 2. The high voltage generator must be disabled (VPR = 0 and PRS = 0) when pad VLCDIN is being driven. 2004 Mar 05 55
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
17.9 Programming examples
PCF8813
Table 25 Programming example for PCF8813 with serial interface (3-line serial, 3-line SPI or 4-line SPI) SERIAL BUS BYTE STEP D/C 1 2 start 0 0 0 1 0 0 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SCE is going low function set: PD = 0, V = 0; select extended instruction set (H = 1) set PRS to higher programming range (PRS = 1) set VPR: VPR* = (a + 132* x b) = 8.596 V (required voltage is dependent on liquid crystal operating environment) function set: PD = 0, V = 0; select normal instruction set (H = 0) display control: set normal mode (D = 1 and E = 0) set data order: DO = 0 option available in 3-line SPI for setting display data length command (7 shown) data write: Y and X are initialized to 0 by default, so they are not set here
MGS405
DISPLAY
OPERATION
3
0
0
0
0
1
0
0
0
1
4
0
1
0
0
1
0
0
0
0
5
0
0
0
1
0
0
0
0
0
6 7 8
0 0 0 - -
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
0 1 0 0 0 1
1 0 0 0 0 1
1 1 0 0 1 1
0 1 0 0 1 1
0 0 0 0 1 1
9
1
10
1
0
0
0
0
0
1
0
1
data write
MGS406
11
1
0
0
0
0
0
1
1
1
data write
MGS407
12
1
0
0
0
0
0
0
0
0
data write
MGS407
13
1
0
0
0
1
1
1
1
1
data write
MGS409
2004 Mar 05
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
SERIAL BUS BYTE STEP D/C 14 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 0 data write DISPLAY OPERATION
MGS410
15
1
0
0
0
1
1
1
1
1
data write
MGS411
16
0
0
0
0
0
1
1
0
1
display control: set inverse video mode (D = 1 and E = 1)
MGS412
17
0
1
0
0
0
0
0
0
0
set X address of RAM: set address to `0000000'
MGS412
18
1
0
0
0
0
0
0
0
0
data write
MGS414
Table 26 Programming example for PCF8813 with I2C -bus SERIAL BUS BYTE STEP D/C 1 2 3 - - DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 0 1 0 SA1 0 SA0 0 0 0 slave address for write control byte with cleared CO bit and D/C set to logic 0 function set: PD = 0, V = 0; select extended instruction set (H = 1) set PRS to higher programming range (PRS = 1) set VPR: VPR* = (a + 132* x b) = 8.596 V (required voltage is dependent on liquid crystal operating environment) function set: PD = 0; V = 0; select normal instruction set (H = 0) I2C-bus start DISPLAY OPERATION
4
-
0
0
1
0
0
0
0
1
5
-
0
0
0
1
0
0
0
1
6
-
1
0
0
1
0
0
0
0
7
-
0
0
1
0
0
0
0
0
2004 Mar 05
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
SERIAL BUS BYTE STEP D/C 8 9 10 - - - - DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 1 0 I2C-bus 1 0 0 start 1 1 1 0 1 0 0 0 0 display control: set normal mode (D = 1 and E = 0) display configuration (DO = 0) restart: to write into the display RAM the D/C must be set to logic 1, therefore a control byte is needed SA1 0 SA0 0 0 0 slave address for write control byte with cleared CO bit and D/C set to logic 1 data write: Y and X are initialized to 0 by default, so they are not set here
MGS405
DISPLAY
OPERATION
11 12
- -
0 0
1 1
1 0
1 0
1 0
13
1
0
0
0
1
1
1
1
-
14
1
0
0
0
0
0
0
1
-
data write
MGS406
15
1
0
0
0
0
0
1
1
-
data write
MGS407
16
1
0
0
0
0
0
0
0
-
data write
MGS407
17
1
0
0
0
1
1
1
1
-
data write
MGS409
18
1
0
0
0
0
0
1
0
-
data write
MGS410
19
1
0
0
0
1
1
1
1
-
data write
MGS411
20 21 22 - - 0 1 1
I2C-bus start 1 1 1 SA1 SA0 0
restart slave address for write control byte with set CO bit and D/C set to logic 0 58
2004 Mar 05
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
SERIAL BUS BYTE STEP D/C 23 - DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 1 display control: set inverse video mode (D = 1 and E = 1)
MGS412
DISPLAY
OPERATION
24 25
- -
1 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
control byte with set CO bit and D/C set to logic 0 Set X address of RAM: set address to 0000000
MGS412
26 27
- -
1 0
1 0
0 0
0 0
0 0
0 0
0 0
0 0
control byte with set CO bit and D/C set to logic 1 data write
MGS414
28 29
- -
1 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
control byte with set CO bit and D/C set to logic 0 set X address of RAM: set address to 0000000
MGS414
30 31 32 33 - - - 0 1 1 1 1 1
I2C-bus 1 0 1 1 0 1
start 1 0 1 SA1 0 0 SA0 0 0 0 0 0
restart slave address for write control byte with set CO bit and D/C set to logic 1 write data
MGS414
34
-
1
0
0
0
0
0
0
0
control byte with set CO bit and D/C set to logic 0
2004 Mar 05
59
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
18 APPLICATION INFORMATION For additional application information, refer to application note "AN10170". 18.1 Protection from light 18.2 Application examples
PCF8813
In the following application examples, the required minimum values of the external capacitors are: * CVLCD = 100 nF minimum * CVDD, CVDD1 and CVDD2 = 1 F minimum * Higher capacitor values are recommended for ripple reduction.
Semiconductors are light-sensitive. Exposure to light sources can cause malfunctions, therefore the IC should be protected from light in the application. Light protection needs to be applied to all sides of the IC (front, rear and all edges).
handbook, full pagewidth
DISPLAY 102 x 68 pixels
32
102 VLCDSENSE VLCDOUT VLCDIN
36
VDD2, 3 VDD1
PCF8813
VSS1 VSS2 CVDD VSS
CVLCD I/O VDD
MGU647
Fig.51 Application example using the internal charge pump and a single VDD source.
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, full pagewidth
DISPLAY 102 x 68 pixels
32
102
36
VDD2, 3
PCF8813
VDD1 VSS1 VSS2 CVDD2
C VDD1 VDD1 I/O VDD2
CVLCD VSS
MGU648
Fig.52 Application example using the internal charge pump and two separate VDD sources (VDD1 and VDD2).
handbook, full pagewidth
DISPLAY 102 x 68 pixels
32
102
VLCDSENSE VLCDOUT VLCDIN
36
VLCDSENSE
VDD2, 3 VDD1
PCF8813
VSS1 VSS2
VLCDOUT
I/O
CVDD VDD VSS VLCDIN
MGU649
Fig.53 Application example using external high voltage generation.
2004 Mar 05
61
VLCDIN
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
19 DEVICE PROTECTION DIAGRAM
PCF8813
handbook, full pagewidth
VDD1
VDD2
VDD3
VSS1
VSS1 VSS2
VSS1
VSS2
VLCDIN , VLCDSENSE
VLCDOUT
VSS1 VSS1
VSS1
VOTPPROG
VLCDIN
VDD1 DB [7:0], SCLK, SDATA, SDO, SA1, SA0, R/W, WR
VSS1
LCD outputs
VSS1
VSS1
VDD1 OSC, RES, RD, D/C, PS [2:0], T1, T2, T5, E VSS1 I2C-bus pins
VDD1
VDD1
T3, T4, VSS1*, VDD* VSS1
VSS1
MGW770
Protection diode maximum forward current = 5 mA.
Fig.54 Protection circuit diagrams.
2004 Mar 05
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Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
20 BONDING PAD INFORMATION
PCF8813
RES VLCDSENSE
VOTPPROG
handbook, full pagewidth
VLCDOUT
VDD1(1)
SCE/SCLH
VLCDIN
(1)
dummy dummy
VDD1 PS [2]
PS [1]
PS [0]
OSC
T8
DC
T3
T4
T2
T1
T5
alignment mark
y
0, 0
x
pad 1
8 Rows R15
8 Rows R0
8 Rows R16
8 Rows R31 C0
32 Columns
32 Columns
dummy alignment & dummy
DB7/SDATA
SDAHOUT
DB6/SCLK
DB5/SD0
DB3/SA1
DB2/SA0
R/W/WR
VDD1(1)
VDD2
VDD3
VDD1
VSS1(1)
T8
VSS1
VSS2
E/RD
T8
alignment mark
38 Columns C101 R66
PCF8813
8 Rows R63
8 Rows R48
8 Rows R32
8 Rows R47 R67(2) dummy
R67 (ICON ROW)
alignment & dummy
MGW797
(1) Can be used to tie-off unused input pads to the power supply voltage or to ground. (2) Used only for icons.
Fig.55 Bonding pad locations.
2004 Mar 05
63
dummy dummy
SDAH
DB4
DB1
DB0
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
Table 27 Bonding pad locations All x and y coordinates are referenced to the centre of the chip; dummy bumps should never be connected to any electrical nodes; dimensions in m; see Fig.55. COORDINATES SYMBOL dummy dummy dummy dummy and alignment dummy dummy R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 -5328 -5328 -5274 -5175 -5085 -5031 -4869 -4815 -4761 -4707 -4653 -4599 -4545 -4491 -4437 -4383 -4329 -4275 -4221 -4167 -4113 -4059 -3843 -3789 -3735 -3681 -3627 -3573 -3519 -3465 -3411 -3357 -3303 -3249 -3195 y +814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5
PCF8813
COORDINATES SYMBOL R29 R30 R31 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 PAD x 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 -3141 -3087 -3033 -2871 -2817 -2763 -2709 -2655 -2601 -2547 -2493 -2439 -2385 -2331 -2277 -2223 -2169 -2115 -2061 -2007 -1953 -1899 -1845 -1791 -1737 -1683 -1629 -1575 -1521 -1467 -1413 -1359 -1305 -1251 -1197 -1035 -981 -927 -873 y -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5
2004 Mar 05
64
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
COORDINATES SYMBOL C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 PAD x 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 -819 -765 -711 -657 -603 -549 -495 -441 -387 -333 -279 -225 -171 -117 -63 -9 +45 +99 +153 +207 +261 +315 +369 +423 +477 +531 +585 +639 +801 +855 +909 +963 +1017 +1071 +1125 +1179 +1233 +1287 +1341 y -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 R67 R66 R65 R64 R63 R62 R61 R60 R59 R58 R57 R56 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 SYMBOL PAD
COORDINATES x +1395 +1449 +1503 +1557 +1611 +1665 +1719 +1773 +1827 +1881 +1935 +1989 +2043 +2097 +2151 +2205 +2259 +2313 +2367 +2421 +2475 +2529 +2583 +2637 +2691 +2745 +2799 +2961 +3015 +3069 +3123 +3177 +3231 +3285 +3339 +3393 +3447 +3501 +3555 y -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5
2004 Mar 05
65
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
COORDINATES SYMBOL R55 R54 R53 R52 R51 R50 R49 R48 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R67 dummy and alignment dummy dummy dummy dummy SDAHOUT SDAH SDAH VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 2004 Mar 05 PAD x 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 +3609 +3663 +3717 +3771 +3825 +3879 +3933 +3987 +4203 +4257 +4311 +4365 +4419 +4473 +4527 +4581 +4635 +4689 +4743 +4797 +4851 +4905 +4959 +5013 +5067 +5229 +5328 +5328 +5274 +4752 +4500 +4122 +4068 +3528 +3474 +3420 +3366 +3312 +3258 y -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 -814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 66 VDD3 VDD3 VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD1 R/W/WR E/RD DB0 DB1 DB2/SA0 DB3/SA1 DB4 DB5/SDOUT DB6/ SCLK DB7/SDATA VSS1 D/C SCE/SCLH SCE/SCLH VOTPPROG VOTPPROG VOTPPROG VDD1 OSC VSS2 VSS2 VSS2 VSS2 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 SYMBOL PAD
COORDINATES x +3204 +3150 +3096 +3042 +2988 +2934 +2880 +2826 +2772 +2718 +2664 +2610 +2556 +2502 +2448 +2286 +2124 +1962 +1746 +1530 +1314 +1098 +882 +666 +450 +234 +72 -90 -630 -684 -792 -846 -900 -1008 -1296 -1458 -1512 -1566 -1620 y +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
COORDINATES SYMBOL VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 T5 T1 T2 PS0 PS1 PS2 PAD x 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 -1674 -1728 -1782 -1836 -1890 -1944 -1998 -2052 -2106 -2160 -2214 -2268 -2322 -2376 -2430 -2484 -2646 -2808 -2970 -3132 -3294 -3456 y +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 VDD1 T4 T3 VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDSENSE RES dummy 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 SYMBOL PAD
COORDINATES x -3618 -3780 -3942 -3996 -4050 -4104 -4158 -4212 -4266 -4320 -4374 -4428 -4482 -4536 -4590 -4644 -4698 -4752 -4806 -4860 -5076 -5274 y +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5 +814.5
2004 Mar 05
67
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
handbook, halfpage
10.845 mm
PCF8813
handbook, halfpage
1.845 mm
y center
pitch
d
y
x center
MGU651
x
MGU650
d = 90 m; there are two 90 m alignment marks.
Fig.56 Chip dimensions.
Fig.57 Shape of alignment mark.
Table 28 Bump size PARAMETER Bump width Bump length Bump height Minimum pad pitch Pad size, aluminium Maximum wafer thickness, including bumps Typical wafer thickness, without bumps VALUE (m) 32 81 17.5 54 45 x 81 430 381
2004 Mar 05
68
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
21 TRAY INFORMATION
PCF8813
handbook, full pagewidth
x G y H
1,1 1,2
A C
x,1
D
B
F
1,y
x,y
A K L
E M
A
J SECTION A-A
MGW798
Fig.58 Tray details.
Table 29 Tray dimensions DIMS A B C D E F G H J K L M x y DESCRIPTION pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction tray width; x direction tray width; y direction distance from cut corner to pocket (1, 1) centre distance from cut corner to pocket (1, 1) centre tray thickness tray cross section tray cross section pocket depth number of pockets in x direction number of pockets in y direction VALUE 14.66 mm 3.76 mm 10.95 mm 1.95 mm 50.8 mm 50.8 mm 10.74 mm
MGW799
PCF8813
handbook, halfpage
4.72 mm 3.96 mm 1.78 mm 2.44 mm 0.89 mm 3 12 69
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
Fig.59 Tray alignment.
2004 Mar 05
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
22 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
PCF8813
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 23 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 24 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Mar 05
70
Philips Semiconductors
Product specification
(67 + 1) x 102 pixels matrix LCD driver
PCF8813
Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 25 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2004 Mar 05
71
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R15/02/pp72
Date of release: 2004
Mar 05
Document order number:
9397 750 12934

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